Edge termination structures are commonly utilized in semiconductor wafers for balancing the electric field on the peripheral regions of one or more active cells. In absence of an appropriate edge termination structure, the presence of corners and curvatures of doped regions with an increased density of equipotential lines may substantially increase the possibility of breakdown of the semiconductor material in the peripheral regions.
A conventional edge termination structure may include a field plate overlying a thick field oxide layer on a top surface of a semiconductor substrate, and a junction termination extension under the thick field oxide. Due to the presence of the thick field oxide over the semiconductor substrate, a thick photoresist mask is required to cover both the thick field oxide and the field plate during a subsequent photolithographic process to print or pattern features, such as gate trenches, in the active cells of the semiconductor substrate. The thick photoresist mask may adversely affect the optical resolution of the photolithographic process, which may result in large active cell features in the semiconductor substrate. Large active cell features may adversely affect device performance, such as increasing on-resistance and limiting switching speed. In addition, because the thick field oxide layer is situated above the top surface of the semiconductor substrate, more than one layer of conductive material may be required to form the field plate, thereby increasing manufacturing cost.
Thus, there is a need in the art for a planar edge termination structure that can effectively lower the electric field to prevent breakdown at the edges of a semiconductor substrate, while allowing active cells in the semiconductor substrate to achieve smaller feature sizes, reduced on-resistance and faster switching speed.